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| pfs704-729eg hiperpfs ? family www.powerint.com november 2010 high power pfc controller with integrated high-voltage mosfet key benefts ? single chip solution for boost power factor correction (pfc) ? en61000-3-2 class c and d compliant ? high light load effciency at 10% and 20% load ? >95% effciency from 10% load to full load ? <130 mw no-load consumption at 230 vac with output in regulation ? <50 mw no-load consumption at 230 vac in remote off state ? frequency adjusted over line voltage, and line cycle ? spread-spectrum across >60 khz window to simplify emi fltering requirements ? lower boost inductance ? provides up to 1 kw peak output power ? >1 kw peak power delivery in power limit voltage regulation mode ? high integration allows smaller form factor, higher power density designs ? incorporates control, gate driver, and high-voltage power mosfet ? internal current sense reduces component count and system losses ? protection features include: uv, ov, otp, brown-in/out, cycle- by-cycle current limit, and power limiting for overload protection ? halogen free and rohs compliant applications ? pc ? high power adaptors ? printer ? high power led lighting ? lcd tv ? industrial and appliance ? video game consoles ? generic pfc converters figure 1. typical application schematic. output power table product maximum continuous output power rating at 90 vac peak output power rating at 90 vac pfs704eg 110 w 120 w pfs706eg 140 w 150 w pfs708eg 190 w 205 w pfs710eg 240 w 260 w pfs712eg 300 w 320 w pfs714eg 350 w 385 w pfs716eg 388 w 425 w product maximum continuous output power rating at 180 vac peak output power rating at 180 vac pfs723eg 255 w 280 w pfs724eg 315 w 350 w pfs725eg 435 w 480 w pfs726eg 540 w 600 w PFS727EG 675 w 750 w pfs728eg 810 w 900 w pfs729eg 900 w 1000 w table 1. output power table (see notes on page 9) pi-6021-110810 d s fb vcc vcc v g ac in dc out control + hiperpfs
rev. a 11/09/10 2 pfs704-729eg www.powerint.com section list description .................................................................................................................................................................. 3 product highlights ...................................................................................................................................................... 3 pin functional description ......................................................................................................................................... 4 pin confguration ...................................................................................................................................................... 4 functional block diagram ........................................................................................................................................ 4 functional description ............................................................................................................................................... 5 output power table ................................................................................................................................................. 9 application example ............................................................................................................................................ 10-11 design, assembly, and layout considerations .................................................................................................... 12 absolute maximum ratings ..................................................................................................................................... 19 parameter table ................................................................................................................................................ 19-25 typical performance characteristics ...................................................................................................................... 26 package details ........................................................................................................................................................ 27 part ordering information ......................................................................................................................................... 28 part marking information ......................................................................................................................................... 28 rev. a 11/09/10 3 pfs704-729eg www.powerint.com description the hiperpfs device family members incorporate a continuous condition mode (ccm) boost pfc controller, gate driver, and high voltage power mosfet in a single, low-profle esip? power package that is able to provide near unity input power factor. the hiperpfs devices eliminate the pfc converters need for external current sense resistors, the power loss associated with those components, and leverages an innovative control technique that adjusts the switching frequency over output load, input line voltage, and even input line cycle. this control technique is designed to maximize effciency over the entire load range of the converter, particularly at light loads. additionally, this control technique signifcantly minimizes the emi fltering requirements due to its wide-bandwidth spread spectrum effect. hiperpfs includes power integrations standard set of comprehensive protection features, such as integrated soft-start, uv, ov, brown-in/out, and hysteretic thermal shutdown. hiperpfs also provides cycle-by-cycle current limit for the power mosfet, power limiting of the output for over-load protection, and pin-to-pin short-circuit protection. hiperpfss innovative variable-frequency continuous conduction mode of operation (vf-ccm) minimizes switching losses by maintaining a low average switching frequency, while also varying the switching frequency in order to suppress emi, the traditional challenge with continuous-conduction-mode solutions. systems using hiperpfs typically reduce the total x and y capacitance requirements of the converter, the inductance of both the boost choke and emi noise suppression chokes, reducing overall system size and cost. additionally, compared with designs that use discrete mosfets and controllers, hiperpfs devices dramatically reduce component count and board footprint while simplifying system design and enhancing reliability. the innovative variable-frequency, continuous conduction mode controller enables the hiperpfs to realize all of the benefts of continuous-conduction mode operation while leveraging low-cost, small, simple emi flters. many regions mandate high power factor for many electronic products with high power requirements. these rules are combined with numerous application-specifc standards that require high power supply effciency across the entire load range, from full load to as low as 10% load. high effciency at light load is a challenge for traditional pfc approaches in which fxed mosfet switching frequencies cause fxed switching losses on each cycle, even at light loads. hiperpfs simplifes compliance with new and emerging energy-effciency standards over a broad market space in applications such as pcs, lcd tvs, notebooks, appliances, pumps, motors, fans, printers, and led lighting. hiperpfs advanced power packaging technology and high effciency simplifes the complexity of mounting the package and thermal management, while providing very high power capabilities in a single compact package; these devices are suitable for pfc applications from 75 w to 1 kw product highlights protected power factor correction solution ? incorporates high-voltage power mosfet, controller, and gate driver ? en61000-3-2 class d compliance ? integrated protection features reduce external component count ? accurate built-in brown-in/out protection ? accurate built-in undervoltage (uv) protection ? accurate built-in overvoltage (ov) protection ? hysteretic thermal shutdown (otp) ? internal power limiting function for overload protection ? cycle-by-cycle power switch current limit ? no external current sense required ? provides lossless internal sensing via sense-fet ? reduces component count and system losses ? minimizes high current gate drive loop area ? minimizes output overshoot and stresses during start-up ? integrated power limit and frequency soft start ? improve dynamic response ? input line feed-forward gain adjustment for constant loop gain across entire input voltage range ? eliminates up to 40 discrete components for higher reliability and lower cost intelligent solution for high effciency and low emi ? continuous conduction mode pfc uses novel constant volt/ amp-second control engine ? high effciency across load using a uf boost diode ? low cost emi flter ? universal input device (pfs704 C pfs716) utilize frequency sliding technique for light load effciency improvements ? >95% effciency from 10% load to full load at low line input voltage ? >96% effciency from 10% load to full load at high line input voltage ? high line input device (pfs723 C pfs729) maintain higher average switching frequency to minimize boost inductance and core size ? >94% effciency from 10% load to full load ? variable switching frequency to simplify emi flter design ? varies over line input voltage to maximize effciency and minimize emi flter requirements ? varies with input line cycle voltage by >60 khz to maximize spread spectrum effect advanced package for high power applications ? up to 1 kw peak output power capability in a highly compact package ? simple clip mounting to heat sink ? can be directly connected to heat sink with insulation pad ? provides thermal impedance equivalent to a to-220 ? staggered pin arrangement for simple routing of board traces and high voltage creepage requirements ? single package solution for pfc converter reduces assembly costs and layout size rev. a 11/09/10 4 pfs704-729eg www.powerint.com figure 3. functional block diagram. pin functional description voltage monitor (v) pin: the v pin is tied to the rectifed ac rail through an external resistor. internal circuitry detects the peak of the input line voltage which resembles a full-wave rectifed waveform. the rectifed high-voltage bus is connected directly to the v pin voltage through a large resistor (4 m w for pfs70x and pfs71x; 9 m w for pfs72x) to minimize power dissipation and standby power consumption. a small ceramic capacitor (0.1 m f for pfs70x and pfs71x; 0.047 m f for pfs72x) is required from the voltage monitor pin to signal ground pin to bypass any switching noise present on the rectifed bus. this pin also features both brown-in and brown-out protection. feedback (fb) pin: the feedback pin is high input-impedance reference terminal that connects to a feedback resistor network. this pin will also feature fast overvoltage and undervoltage detection circuitry that will disengage the internal power mosfet in the event of a system fault. a 10 nf capacitor is required between the feedback to signal ground pins; this capacitor must be placed very close to the device on the pcb to bypass any switching noise. this pin is also used for loop compensation. bias power (vcc) pin: this is a 10-12 vdc bias supply used to power the ic. the bias voltage must be externally clamped to prevent the vcc pin from exceeding 13.4 vdc. signal ground (g) pin: discrete components used in the feedback circuit, including loop compensation, decoupling capacitors for the supply (vcc) and line-sense (v) must be referenced to the g pin. the signal ground pin must not be tied to the source pin . source (s) pin: this pin is the source connection of the power switch. drain (d) pin: this is the tab and drain connection of the internal power switch. figure 2. pin confguration. pi-5333-113010 + - + - + - + - off-time derived with constant volt-sec input voltage emulation v off is a function of the error-voltage (v e ) and is used to reduce the average operating frequency as a function of output power for increased efficiency (pfs704-716). (v off = 0.8 v for pfs723-729). the internal derived error-voltage (v e ) regulates the output voltage m on is the switch current sense scale factor which is function of peak line voltage derived from i vin fast ov comparator fb ov/uv otp v cc voltage monitor (v) signal ground (g) source (s) bias power (vcc) drain (d) feedback (fb) fb uv / fb off v cc+ m on internal reference v ref transconductance error-amplifier driver i ocp sense fet power mosfet uv comparator timer supervisor input line interface peak detector internal supply otp soft start + - + - + - + - 6 v c int m on i s c int v o -v in i vpk i vpk input uv (i uv- /i uv+ ) i s leb ocp 1 khz filter 7 khz filter comparator v off v off v e v e frequency slide comparator latch input uv fb ov pi-5334-083110 exposed pad (backside) internally connected to drain pin (see esip-7g package drawing) exposed metal (on edge) internally connected to drain pin exposed metal (on edge) internally connected to ground pin e package (esip-7g) 1 2 3 4 5 7 v fb vcc g s d 7 5 4 3 2 1 d s g vcc fb v rev. a 11/09/10 5 pfs704-729eg www.powerint.com functional description the hiperpfs is a variable switching frequency boost pfc solution. more specifcally, it employs a constant amp-second on-time and constant volt-second off-time control algorithm. this algorithm is used to regulate the output voltage and shape the input current to comply with regulatory harmonic current limits (high power factor). integrating the switch current and controlling it to have a constant amp-sec product over the on-time of the switch allows the average input current to follow the input voltage. integrating the difference between the output and input voltage maintains a constant volt-second balance dictated by the electro-magnetic properties of the boost inductor and thus regulates the output voltage and power. more specifcally, the control technique sets constant volt- seconds for the off-time (t off ). the off-time is controlled such that: (1) since the volt-seconds during the on-time must equal the volt-seconds during the off-time, to maintain fux equilibrium in the pfc choke, the on-time (t on ) is controlled such that: (2) the controller also sets a constant value of charge during each on-cycle of the power mosfet. the charge per cycle is varied gradually over many switching cycles in response to load changes so it can be regarded as substantially constant for a half line cycle. with this constant charge (or amp-second) control, the following relationship is therefore also true: (3) substituting t on from (2) into (3) gives: (4) the relationship of (4) demonstrates that by controlling a constant amp-second on-time and constant volt-second off-time, the input current i in is proportional to the input voltage v in , therefore providing the fundamental requirement of power factor correction. this control produces a continuous mode power switch current waveform that varies both in frequency and peak current value across a line half-cycle to produce an input current proportional to the input voltage. control engine the controller features a low bandwidth error-amplifer which connects its non-inverting terminal to an internal voltage reference of 6 v. the inverting terminal of the error-amplifer is available on the external feedback pin which connects to the external feedback resistor divider, transient load speed-up and compensation networks to regulate the output voltage. the internal sense-fet switch current is integrated and scaled by the input voltage peak detector current sense gain (m on ) and compared with the error-amplifer signal (v e ) to determine the cycle on-time. internally the difference between the input and output voltage is derived and the resultant is scaled, integrated, and compared to a voltage reference (v off ) to determine the cycle off-time. careful selection of the internal scaling factors produce input current waveforms with very low distortion and high power factor. the input voltage is internally synthesized using the switch duty cycle and a 7 khz low pass flter. this synthesized input voltage representation is subtracted from a fxed reference voltage (6 v) to derive a current source proportional to (v o -v in ). please refer to figure 3. line feed-forward scaling factor (m on ) the voltage monitor (v) pin current is used internally to derive the peak of the input line voltage which is used to scale the gain of the current sense signal through the m on variable. this contribution is required to reduce the dynamic range of the control feedback signal as well maintain a constant loop gain over the operating input line range. this line-sense feed- forward gain adjustment is proportional to the square of the peak rectifed ac line voltage and is adjusted as a function of v pin current. the line-sense feed-forward gain is also important in providing a switch power limit over the input line range. besides modifying brown- in/out thresholds, the v pin resistor also affects power limit of the device this characteristic is optimized to maintain a relatively constant internal error-voltage level at full load from an input line of 100 to 230 vac input (pfs704-716). beyond the specifed peak power rating of the device, the internal power limit feature will regulate the output voltage below the set regulation threshold as a function of output overload beyond the peak power rating. figure 5 illustrates the typical regulation characteristic as function of load. soft-start with pin-to-pin short-circuit protection since the feedback pin is the interface for output voltage regulation (resistor voltage divider to output voltage) as well as loop compensation (series rc), the typical application circuit of the hiperpfs requires an external transistor network to overcome the inherently slow feedback loop response. specifcally, an pi-5335-111610 i s dt v e v off (v out -v in )dt latch reset latch set gate drive (q) maximum on-time minimum off-time timing supervisor figure 4. idealized converter waveforms. rev. a 11/09/10 6 pfs704-729eg www.powerint.com soft-start check sequence start converter is v cc > v cc+ apply 0.5 a on fb to check open fb apply 6 ma v pin current sink is v fb > fb off is v fb > fb off and v fb < fb ov no yes yes yes no no pi-5337-110910 yes no is i v > i uv+ remove 6 ma v pin current sink detect input v oltage peak slew power-limit over soft-start duration npn and pnp transistor are tied between the output voltage divider resistors to limit the maximum overshoot and under- shoot during a load transient response. to reduce switch and output diode current stress at start-up, the hiperpfs slews the internal error-voltage from zero to its steady-state value at start-up. figure 6 illustrates the relative relationship between the application of v cc and power limit soft-start function through the internal error-voltage. the error-voltage has a controlled slew rate of 0.25 v/ms at start-up, corresponding to the t soft time duration for a full scale error voltage of 5 v. the beginning of soft-start is gated by the v cc+ , i uv+ and feedback pin voltage thresholds in the sequence described below. once the applied v cc is above the v cc+ threshold, the sensed v pin current is above i uv+ and the feedback pin voltage is above fb off , the ic applies a ~6 ma current sink through the voltage monitor pin and checks that the feedback pin voltage is still above the fb off threshold. this checks to ensure that the feedback and v pins are not shorted together. in the event that the feedback pin voltage is below the fb off pi-5336-110810 internal error-voltage (v e ) v cc voltage t start-delay t soft v cc+ t ~5 v threshold the v pin holds the 6 ma current sink indefnitely until the feedback pin is above the fb off . if the feedback pin voltage is above fb off , the ic releases the current source and resumes with normal soft-start and operation. figure 7 illustrates this sequence. timing supervisor and operating frequency range since the controller is expected to operate with a variable switching frequency over the line frequency half-cycle, typically spanning a range of 24 C 95 khz, the controller also features a timing supervisor function which monitors and limits the maximum switch on-time and off-time as well as ensures a minimum cycle off-time. the timer supervisor limits the normal operating frequency range for loads in excess of 10% of the device peak power rating. figure 8a shows the typical half-line frequency profle of the device switching frequency as a function of input voltage at peak load conditions. figure 8b shows for a given line condition the effect of ecosmart to the switching frequency as a function of load (pfs704-716). the switching frequency is not a function of boost choke inductance. ecosmart the pfs704-716 controllers includes an ecosmart mode wherein the internal error signal (v e ) is used to detect the converter output power. since the internal error-signal is directly proportional to the output power, this signal level is used to set the average switching frequency as a function of output power. the off-time integrator control reference (v off ) is figure 7. start-up sequence. figure 5. typical normalized output voltage characteristics as function of normalized peak load rating figure 6. power limit soft-start function. 0 0.2 0.4 0.6 1 1.2 1.4 0.8 normalized to peak power rating normalized to set output voltage regulation threshold 1.2 1 0.8 0.6 0.4 0.2 0 pi-6216-113010 rev. a 11/09/10 7 pfs704-729eg www.powerint.com pi-5338-110810 v off v e ~5 v (full power) ~4.8 v pfs704-716 v in < 140 vac pfs704-716 pfs704-716 v in > 170 vac pfs723-729 ~5 v ~2.5 v ~0.8 v v off at v e = 0 v v in ~170 vac ~140 vac ~5 v ~2.5 v controlled with respect to the internal error-voltage level (output power) to allow the converter to maintain output voltage regulation and relatively fat conversion effciency between 10% to 100% of rated load which is essential to meet many effciency directives. the degree of frequency slide is also controlled as a function of peak input line voltage, at high input line the maximum off-time voltage reference at zero error-voltage will be approximately 1/2 of the maximum value at low input line conditions. the lower v off slope reduces the average frequency swing for high input line operation. the pfs723-729 does not reduce the average frequency as a function of load (v off is a constant value of ~0.8 v). protection modes voltage monitor (v) pin shutdown the voltage monitor pin features a shutdown protection mode which can be used with the voltage monitor pin resistor or external circuitry to cover system faults. during start-up (1 v < v fb < 5.8 v) in the event the current through the voltage monitor pin exceeds the i v(off) threshold for a duration exceeding approximately (1 m s), the ic disables the internal mosfet for the entire duration that the v pin current is above i v(off) . in normal operation, if the current through the v pin exceeds the i v(off) threshold for a duration exceeding t v(off) , the ic will reinitiate the start-up sequence. brown-in protection (i uv+ ) the voltage monitor pin features an input line undervoltage detection to limit the minimum start-up voltage detected through the v pin. this detection threshold will inhibit the device from starting at very low input ac voltage. brown-out protection (i uv- ) the v pin features a brown-out protection mode wherein the hiperpfs will turn-off when the v pin current is below the line uv-threshold for a period exceeding the t refresh time period. in the event a single half-line cycle is missing (normal operating figure 8. (a) frequency variation over line half-cycle as a function of input voltage (b) frequency variation over line half-cycle as a function of load. figure 9. v off vs. v e and v off vs. input voltage. 0 45 90 135 180 pi-6217-110110 120 230 vac 180 vac 135 vac 115 vac peak load 90 vac 110 100 90 80 70 60 50 40 30 20 10 frequency (khz) line conduction angle (c) 0 45 90 135 180 pi-6218-102910 120 110 100 90 80 70 60 50 40 30 20 10 frequency (khz) line conduction angle (c) 100% peak load 75% peak load v in = 115 vac 25% peak load 50% peak load expected frequency range at peak rated load rev. a 11/09/10 8 pfs704-729eg www.powerint.com pi-5470-110810 i ocp ~170 vac pfs704-716 v in ~140 vac i v < 48 a i v > 59 a figure 10. line dependant ocp. line frequency is 47 to 63 hz) the brown-out protection will not be activated. the hiperpfs shutdown in effect gradually reduces the internal error-voltage to zero volts at rate of 1 v/ms to decay the power mosfet on-time to zero. at peak power (v e ~5 v) the shutdown time will be approximately 5 ms. the internal error-voltage is held at 0 v for as long as the input peak voltage is below the brown-in (i uv+ ) threshold. the internal error-voltage controlled slew to 0 v gradually reduces the switch on-time to zero to deplete energy stored in the boost choke as well as input emi flter for power-down. once the error-voltage reaches zero volts the controller is effectively in an off-state (gated by 5 ms timer) and will restart once all the conditions of soft-start are satisfed. the brown-out threshold is reduced to i uv-ss during start-up until the feedback pin exceeds approximately 5.8 v. temporarily reducing the brown-out threshold prevents false turn-off at high power start-up when the voltage drop across the input bridge rectifer and flter stage may cause the rectifed input to sag below the brown-out threshold. fast output voltage overvoltage protection (fb ov ) the feedback pin features a means to detect an output overvoltage condition through the feedback pin and disables the power mosfet until the sensed output voltage falls below the fb ov threshold. a deglitch flter (~2 m s) is used to prevent the controller from falsely triggering this mode. an fb ov event in excess of the 2 m s delay will terminate the switch cycle immediately. this detection circuit also includes some hysteresis. output voltage undervoltage protection (fb uv ) the feedback pin features an undervoltage detection to detect an output overload or a broken feedback loop. if the ic detects the falling edge on the feedback pin that has fallen below fb uv threshold, it will turn-off the internal power mosfet and reinitiate the start-up sequence. similar to the fb ov detection, this mode has a deglitch flter of approximately 100 m s. vcc undervoltage protection (uvlo) the bias power (vcc) pin has an undervoltage lock-out protection which inhibits the ic from starting unless the applied v cc voltage is above the v cc+ threshold. the ic initiates a soft-start once the vcc pin voltage exceeds the v cc+ threshold. after start-up the ic will continue to operate until the vcc pin voltage has fallen below v cc- level. the absolute maximum voltage of the vcc pin is 13.4 v which must be externally limited to prevent damage to the ic. over-current protection the device includes a cycle-by-cycle over-current-protection (ocp) mode which protects the device in the event of a catastrophic fault. the ocp mode in the pfs704-716 is input line dependent as shown in figure 10. the intention of ocp in this device is strictly protection of the internal power mosfet and is not intended to protect the converter from output short-circuit or overload fault conditions. the pfs704-716 controller latches the high line ocp for a 1/2 line cycle and updates the ocp status after the expiration of a 5 ms block-out timer. this feature has particular beneft for hard-start after an ac line cycle drop where the peak detector may falsely detect a low input line condition even though the input is at high input line. the leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time must be set so that current spikes caused by capacitance and rectifer reverse recovery time will not cause premature termination of the mosfet conduction. safe operating range (soa) mode since the cycle-by-cycle ocp mechanism described above does not prevent the possibility of inductor current stair- casing, an soa mode is required. rapid build up of the device current can occur in event of inductor saturation or when the input and output voltages are equal (non or very short inductor reset time). the soa mode is triggered whenever the device reaches current limit (i ocp ) and the on-time is less than t soa . the soa mode forces an off-time equal to t ocp and pulls the internal error-voltage (v e ) down to approximately 1/2 of its set value. open feedback pin protection the feedback pin also features a static current of i fb that is continuously sourced out of the pin to protect against a fault related to an open feedback pin. the internal current source introduces a static offset to the output regulation which must be accounted for in selecting the output feedback regulation components. hysteretic thermal shutdown the thermal shutdown circuitry senses the controller die temperature. the threshold is set at 118 c typical with a 50 c hysteresis. when the die temperature rises above this threshold (118 c +8/-7 c), the power mosfet switching is disabled and remains disabled until the die temperature falls by ~50 c, at which point the device will reinitiate a soft-start and start-up sequence. rev. a 11/09/10 9 pfs704-729eg www.powerint.com output power table 1 product maximum continuous output power rating at 90 vac 2 peak output power rating at 90 vac 5 product maximum continuous output power rating at 180 vac 4 peak output power rating at 180 vac 5 minimum 3 maximum pfs704eg 85 w 110 w 120 w pfs723eg 255 w 280 w pfs706eg 105 w 140 w 150 w pfs724eg 315 w 350 w pfs708eg 140 w 190 w 205 w pfs725eg 435 w 480 w pfs710eg 180 w 240 w 260 w pfs726eg 540 w 600 w pfs712eg 225 w 300 w 320 w PFS727EG 675 w 750 w pfs714eg 265 w 350 w 385 w pfs728eg 810 w 900 w pfs716eg 295 w 388 w 425 w pfs729eg 900 w 1000 w table 2. output power table. notes: 1. see key application considerations. 2. maximum practical continuous power at 90 vac in an open-frame design with adequate heat sinking, measured at 50 c ambient. 3. recommended lower range of maximum continuous power for best light load effciency ; hiperpfs will operate and perform below this level. 4. maximum practical continuous power at 180 vac in an open-frame design with adequate heat sinking, measured at 50 c ambient. 5. internal output power limit. rev. a 11/09/10 10 pfs704-729eg www.powerint.com application example a high effciency, 347 w, 380 vdc universal input pfc the circuit shown in figure 11 is designed using a pfs714eg device from the hiperpfs family of integrated pfc controllers. this design is rated for a continuous output power of 347 w and provides a regulated output voltage of 380 vdc nominal maintaining a high input power factor and overall effciency from light load to full load. fuse f1 provides protection to the circuit and isolates it from the ac supply in case of a fault. diode bridge br1 rectifes the ac input. capacitors c3, c4, c5, c6 and c19 together with inductors l1, l2, l3 and l4 form the emi flter reducing the common mode and differential mode noise. resistors r1, r3 and capzero, ic u2 are required to discharge the emi flter capacitors once the circuit is disconnected. capzero eliminates static losses in r1 and r2 by only connecting these components across the input when ac is removed. the boost converter stage consists of inductor l5, diode rectifer d2 and the hiperpfs ic u1. this converter stage works as a boost converter and controls the input current of the power supply while simultaneously regulating the output dc voltage. diode d1 prevents a resonant build up of output voltage at start-up by bypassing inductor l5 while simultaneously charging output capacitor c15. thermistor rt1 limits the inrush input current of the circuit at start-up and prevents saturation of l5. in most high-performance designs, a relay will be used to bypass the thermistor after start-up to improve power supply effciency. therefore effciency measurement, that represents the high performance confguration, the thermistors should be shorted. capacitors c14 and c21 are used for reducing the loop length and area of the output circuit to reduce emi and overshoot of voltage across the drain and source of the mosfet inside u1 at each switching instant. the pfs714eg ic requires a regulated supply of 12 v for operation and must not exceed 13.4 v. resistors r6, r16, r17, zener diode vr1, and transistor q3 form a shunt regulator that prevents the supply voltage to ic u1 from exceeding 12 v. capacitors c8, c18 and c20 flter the supply voltage and provide decoupling to ensure reliable operation of ic u1. diode d5 prevents destruction of u1 if the auxiliary input is inadvertently connected reverse polarity. the rectifed ac input voltage of the power supply is sensed by ic u1 using resistors r4, r5 and r19. the capacitor c12 flters any noise on this signal. divider network comprising of resistors r9, r10, r11, r12, r13, and r14 are used to scale the output voltage and provide feedback to ic u1. the circuit comprising of diode d4, transistor q1, q2 and the resistors r12 and r13 form a non- linear feedback circuit which improves the load transient response by improving the response time of the pfc circuit. resistor r7, r8, r15, and capacitors c13 and c17 are required for shaping the loop response of the feedback network. the combination of resistor r8 and capacitor c13 provide a low frequency zero and the resistor r15 and capacitor c13 form a low frequency pole. pi-6197-111110 n e l r1 220 k rt1 10 r6 100 c8 47 f 50 v d5 dl4001 vr1 bzx84c12lt1g q3 mmbt4401lt1g r16 100 r17 3.01 k 1% r2 220 k r18 10 2 w l4 ferrite bead r4 1.5 m 1% r19 1.5 m 1% r5 1 m 1% l5 1.38 mh br1 gbu806 600 v d1 1n5408 d4 1n4148 d3 bav116 130 v d2 stth8s06d l1 14 mh c6 100 nf 275 vac c19 1 f 310 v c5 680 pf 250 vac c7 1 f 400 v r13 2.21 k 1% r7 2 k r12 2.21 k 1% r10 1.6 m 1% r11 732 k 1% r9 1.5 m 1% r15 160 k c17 470 pf 100 v c21 10 nf 1 kv c14 10 nf 1 kv c4 680 pf 250 vac c3 680 nf 275 vac f1 6.3 a rv1 320 vac d s fb vcc v g dc out 380 vdc auxiliary power supply control hiperpfs u1 pfs714eg c11 10 nf 50 v c12 100 nf 50 v c18 1 f 25 v c13 4.7 f 25 v c20 100 nf 50 v q1 mmbt4401 t o d1 capzero u2 cap006dg d2 l2 100 h c16 100 nf 200 v r14 57.6 k 1% q2 mmbt4403 l3 100 h c15 270 f 450 v *optional component r8 3.01 k 1% + + figure 11. 347 w pfc using pfs714eg. rev. a 11/09/10 11 pfs704-729eg www.powerint.com figure 12. 180 w pfc using pfs708eg. figure 13. 900 w pfc using pfs729eg. pi-6229-110210 n e l r1 750 k rt1 10 r2 750 k r4 1.5 m 1% r19 1.5 m 1% r5 1 m 1% l5 1.7 mh br1 3kbp06m 600 v d1 1n5408 d4 1n4148 d3 bav116 130 v d2 stth3r06u l1 10 mh c19 220 nf 275 vac c5 100 pf 250 vac c7 470 nf 400 v r13 2.21 k 1% r7 2 k r12 2.21 k 1% r10 1.6 m 1% r11 732 k 1% r9 1.5 m 1% r15 160 k c17 470 pf 100 v c14 10 nf 1 kv c4 100 pf 250 vac c3 220 nf 275 vac f1 3.15 a rv1 320 vac d s fb vcc v g dc out 12 v auxiliary power supply control hiperpfs u1 pfs708eg c11 10 nf 50 v c12 100 nf 50 v c18 1 f 25 v c13 4.7 f 25 v c20 47 f 25 v q1 mmbt4401 t o d1 capzero u2 cap002dg d2 l2 100 h c16 100 nf 200 v r14 57.6 k 1% q2 mmbt4403 c15 150 f 450 v r8 3.01 k 1% + + pi-6230-111110 n e l r1 220 k rt1 10 r2 220 k r18 10 2 w r4 3 m 1% r19 3 m 1% r5 3 m 1% l5 2.04 mh br1 gbu10j 600 v d1 1n5408 d4 1n4148 d3 bav116 130 v d2 stth12r06 l1 14 mh c19 1 f 275 vac c5 680 pf 250 vac c7 1.5 f 400 v r13 2.21 k 1% r7 2 k r12 2.21 k 1% r10 1.6 m 1% r11 732 k 1% r9 1.5 m 1% r15 160 k c17 470 pf 100 v c21 10 nf 1 kv c14 10 nf 1 kv c4 680 pf 250 vac c3 680 nf 275 vac f1 8 a rv1 320 vac d s fb vcc v g dc out l4 ferrite bead l3 100 h control hiperpfs u1 pfs729eg c11 10 nf 50 v c12 47 nf 50 v c18 1 f 25 v c6 100 nf 275 vac c13 4.7 f 25 v c20 100 nf 25 v q1 mmbt4401 t o d1 capzero u2 cap006dg d2 l2 100 h c16 100 nf 200 v r14 57.6 k 1% q2 mmbt4403 c15 820 f 450 v r8 3.01 k 1% + r6 100 c8 47 f 50 v d5 dl4001 vr1 bzx84c12lt1g q3 mmbt4401lt1g r16 100 r17 3.01 k 1% 15 v auxiliary power supply + rev. a 11/09/10 12 pfs704-729eg www.powerint.com design, assembly, and layout considerations power table the data sheet power table as shown in table 2 represents the maximum practical continuous output power based on the following conditions: for the universal input devices (pfs704-716): 1. an input voltage range of 90 vac to 264 vac 2. overall effciency of at least 93% at the lowest operating voltage 3. use of ultrafast recovery diode or high performance diode for pfc output. 4. suffcient heat sinking to keep device temperature 100 oc 5. 380 v to 385 v nominal output for the 230 v only devices (pfs723-729): 1. an input voltage range of 180 vac to 264 vac 2. overall effciency of at least 96% at the lowest operating voltage 3. use of ultrafast recovery diode or high performance diode for pfc output. 4. suffcient heat sinking to keep device temperature 100 oc 5. 380 v to 385 v nominal output operation beyond the limits stated above will require derating. use of a nominal output voltage higher than 390 v is not recommended for hiperpfs based designs. operation at voltages higher than 390 v can result in higher than expected drain-source voltage during line and load transients. hiperpfs selection selection of the optimum hiperpfs part depends on required maximum output power, pfc effciency and overall system effciency (when used with a second stage dc-dc converter), heat sinking constraints, system requirements and cost goals. the hiperpfs part used in a design can be easily replaced with the next higher or lower part in the power table to optimize performance, improve effciency or for applications where there are thermal design constraints. minor adjustments to the inductance value and emi flter components may be necessary in some designs when the next higher or the next lower hiperpfs part is used in an existing design for performance optimization. every hiperpfs family part has an optimal load level where it offers the most value. operating frequency of a part will change depending on load level. change of frequency will result in change in peak to peak current ripple in the inductance used. change in current ripple will affect input pf and total harmonic distortion of input current. input fuse and protection circuit the input fuse should be rated for a continuous current above the input current at which the pfc turns-off due to input under voltage. this voltage is referred to as the brown-out voltage. the fuse should also have suffcient i 2 t rating in order to avoid nuisance failures during start-up. at start a large current is drawn from the input as the output capacitor charges to the peak of the applied voltage. the charging current is only limited by any inrush limiting thermistors, impedance of the emi flter inductors and the forward resistance of the input rectifer diodes. a mov will typically be required to protect the pfc from line surges. selection of the mov rating will depend on the energy level (en1000-4-5 class level) to which the pfc is required to withstand. input emi filter the variable switching frequency of the hiperpfs effectively modulates the switching frequency and reduces conducted emi peaks associated with the harmonics of the fundamental switching frequency. this is particularly benefcial for the average detection mode used in emi measurements. the pfc is a switching converter and will need an emi flter at the input in order to meet the requirements of most safety agency standards for conducted and radiated emi. typically a common mode flter with x capacitors connected across the line will provide the required attenuation of high frequency components of input current to an acceptable level. the leakage reactance of the common mode flter inductor and the x capacitors form a low pass flter. in some designs, additional differential flter inductors may have to be used to supplement the differential inductance of the common mode choke. a flter capacitor with low esr and high ripple current capability should be connected at the output of the input bridge rectifer. this capacitor reduces the generation of the switching frequency components of the input current ripple and simplifes emi flter design. typically, 0.33 m f per 100 w should be used for universal input designs and 0.15 m f per 100 w of output power should be used for 230 vac only designs. it is often possible to use a higher value of capacitance after the bridge rectifer and reduce the x capacitance in the emi flter. regulatory requirements require use of a discharge resistor to be connected across the input (x) capacitance on the ac side of the bridge rectifer. this is to ensure that residual charge is dissipated after the input voltage is removed when the capacitance is higher than 0.1 m f. use of capzero integrated circuits from power integrations, helps eliminate the steady state losses associated with the use of discharge resistors connected permanently across the x capacitors. inductor design it is recommended that the inductor be designed with the maximum operating fux density less than 0.3 t and a peak fux density less than 0.42 t at maximum current limit when a ferrite core is used. if a core made from sendust or mpp is used, the fux density should not exceed 1 t. a powder core inductor will have a signifcant drop in inductance when the fux density approaches 1 t. when operated at the lower end of the input voltage range, the value of k p (the ratio of peak to ripple current) of the drain current at the peak of the input voltage waveform should be rev. a 11/09/10 13 pfs704-729eg www.powerint.com kept below 0.5 for universal input designs and less than 0.7 for 230 v only designs. for high performance designs, use of litz wire is recommended to reduce copper loss due to skin effect and proximity effect. for toroidal inductors the numbers of layers should be less than 3 and for bobbin wound inductors, interlayer insulation should be used to minimize inter layer capacitance. output diode for a 385 v nominal pfc output voltage, use of a diode with 600 v or higher piv rating is recommended. ccm operation with hard switching demands that diodes with low reverse recovery time and reverse recovery charge should be used. the variable frequency ccm operation of hiperpfs reduces diode switching losses as compared to fxed frequency solutions and enables use of easily available high frequency diodes such as the turbo-2 series from stmicroelectronics. diodes with soft recovery characteristics that result in a reduced emi are available from a number of manufacturers. for highly demanding applications such as 80 plus gold power supplies, use of silicon carbide diodes may be considered. these uses will typically provide further full load improvement in effciency. the diodes will be required to have a forward continuous current rating of at least 1.2 a to 1.5 a for every 100 w of output power. output capacitor for a 385 v nominal pfc, use of a electrolytic capacitor with 450 v or higher continuous rating is recommended. the capacitance required is dependent on the acceptable level of output ripple and any hold up time requirements. the equations below provide an easy way to determine the required capacitance in order to meet the hold up time requirement and also to meet the output ripple requirements. the higher of the two values would be required to be used: capacitance required for meeting the hold up requirement is calculated using the equation: c v v p t 2 ( ) _ o ou t o ut mi n ou t h ol d u p 2 2 # # = - c o pfc output capacitance in f. p o pfc output power in watts. t hold-up hold-up time specifcation for the power supply in seconds. v out lowest nominal output voltage of the pfc in volts. v out(min) lowest permissible output voltage of the pfc at the end of hold-up time in volts. capacitance required for meeting the low frequency ripple specifcation is calculated using the equation: c f v i 2 ( ) o l o pf c o m ax # # # # r h d = f l input frequency in hz v o peak-peak output voltage ripple in volts pfc pfc operating effciency i o(max) maximum output current in amps capacitance calculated using the above method should be appropriately increased to account for ageing and tolerances. power supply for the ic a 12 v regulated supply should be used for the hiperpfs. if the v cc exceeds 13.4 v, the hiperpfs may be damaged. in most applications a simple series pass linear regulator made using an npn transistor and zener diode is adequate since the hiperpfs only requires approximately 3.4 ma maximum for its operation. it is recommended that a 1 m f or higher, low esr ceramic capacitor be used to decouple the v cc supply. this capacitor should be placed directly at the ic on the circuit board. line-sense network the line-sense network connected to the v pin provides input voltage information to the hiperpfs. the value of this resistance sets the brown-in and brown-out threshold for the part. a value of 4 m w is recommended for use with the universal input parts and a value of 9 m w is recommended for the 230 vac only parts. only 1% tolerance resistors are recommended. this resistance value may be modifed to adjust the brown-in threshold if required however change of this value will affect the maximum power delivered by the part. a decoupling capacitor of 0.1 m f is required to be connected from the voltage monitor pin to the ground pin of the hiperpfs for the universal input parts and a decoupling capacitor of 0.047 m f is required for the 230 vac only parts. this capacitor should be placed directly at the part on the circuit board. feedback network a resistor divider network that provides 6 v at the feedback pin at the rated output voltage should be used. the compensation elements are included with the feedback divider network since the hiperpfs does not have a separate pin for compensation. the hiperpfs based pfc has two loops in its feedback. it has an inner current loop and a low bandwidth outer voltage loop which ensures high input power factor. the compensation rc circuit included with the feedback network reduces the response time of the hiperpfs to fast changes in output voltage resulting from transient loads. the feedback circuit recommended for use with the hiperpfs includes a pair of transistors that are biased in a way that the transistors are in cutoff during normal operation. when a rapid change occurs in the output voltage, these transistors conduct momentarily to correct the feedback pin voltage rapidly thereby helping the hiperpfs to respond to the changes in output voltage without the delay associated with a low bandwidth feedback loop. the recommended circuit and the associated component values are shown in figure 14. resistors, r1 to r5 comprise of the main output voltage divider network. the sum of resistors r1, r2 and r3 is the upper divider resistor and the lower feedback resistor is comprised of the sum of resistors r4 and r5. capacitor c1 is a soft-fnish capacitor that reduces output voltage overshoot at start-up. resistor r8 and capacitor c3 form a low pass flter to flter any switching noise from coupling into the feedback pin. resistor rev. a 11/09/10 14 pfs704-729eg www.powerint.com pi-6228-111110 d1 d2 r8 r1 r2 r3 r6 q1 q2 r4 r5 d s fb vcc v g control hiperpfs c3 c2 c1 b+ v cc r7 r7 and capacitor c2 is the loop compensation network which introduces a low frequency zero required to tailor the loop response to ensure low cross-over frequency and suffcient phase margin. resistor r6 isolates the fast portion (resistor voltage divider network comprising of resistors r1 to r5) and the slow feedback loop compensator circuit (resistor r7 and capacitor c2). transistors q1 and q2, biased with resistors r3 and r4 respectively, detect output voltage transient conditions and provide the feedback pin with fast information to increase the loop response of the system. diode d1 is included to cover a single point fault condition wherein capacitor c2 is shorted. in the event c2 is short-circuited, the feedback pin is forced below the fb off threshold through diode d1 and subsequently turns the hiperpfs off. only a standard recovery diode should be used for d1. use of ultrafast or fast recovery diode is not recommended including small signal diodes (e.g. 1n4148) which are typically also fast recovery. the recommended values for the components used are as follows: r5 = 57.6 k w r3, r4 = 2.2 k w r2 = 732 k w c1 = 0.1 m f, 100 v x7r/npo r6 = 160 k w r7 = 3 k w r8 = 2 k w c2 = 4.7 m f c3 = 10 nf (for layouts that result in excessive noise on the feedback signal, a 20 nf capacitor may be used). d1 = bav116 w or 1n4007 (a general purpose standard recovery diode should only be used). q1, q2 = small signal transistors equivalent to 2n4401 and 2n4403. figure 14. recommended feedback circuit. when the above component values are used, the value of resistor r1 can be calculated using the equation below: r v 10 0 1 0 79 o 1 6 # = - - since the total voltage across resistor r1 is approximately 301 v, resistor r1 may have to be divided into two or more resistors to distribute the voltage stress below the voltage ratings of the resistor used. the value of resistor r7 will have to be adjusted in some designs and as a guideline the value from the following calculation can be used: r r v c p k 4 z o o o 7 2 # # x = = ^ h p o maximum continuous output power in watts v o nominal pfc output voltage in volts c o pfc output capacitance in farads improvement in low frequency phase margin can be achieved by increasing the value of the capacitor c2 however increase in value of capacitor c2 will result in some increase in overshoot at the output of the pfc during transient loading and should be verifed. diode d2 connected in series with the collector of the npn transistor q1 is to prevent loading of the feedback circuit when the v cc is absent. presence of this diode ensures that there is no start-up delay when the v cc is applied to the hiperpfs, the feedback circuit, and transistor. wp6sw?c ic (w6 cwmdpuh6fwbp>c( the exposed pad on the hiperpfs esip package is internally connected to the drain of the mosfet. due to the signifcant amount of power dissipated in the part, the hiperpfs should be mounted on a rectangular heat spreader made of thermally conductive material such as aluminum or copper. figure 15 shows an example of the recommended assembly for the hiperpfs. in this assembly shown, a 0.76 mm thick aluminum heat spreader is used. a thermally conductive sil pad should be used to separate the heat spreader from the heat sink. a thin flm of thermally conductive silicone grease should be applied to the rear surface of the hiperpfs to ensure low thermal resistance contact between the package of the hiperpfs and the heat spreader. for universal input applications up to 150 w and 230 vac only applications up to 300 w, the heat spreader is not essential. use of heat spreader in these applications will help reduce temperature of the part and heat spreaders can be used if necessary. figure 17 shows an example of the recommended assembly for lower power designs that do not need a heat spreader. the hiperpfs is electrically connected to the heat spreader and the heat sink is required to be connected to the source in order to reduce emi. the voltage between the heat spreader and heat sink can easily exceed 400 v during transient conditions. attention should be placed on creepage and clearance based on applicable safety specifcation. rev. a 11/09/10 15 pfs704-729eg www.powerint.com figure 15. heat sink assembly example C high power designs. figure 16. heat sink assembly C high power designs. 1. screw 2. shoulder washer 3. edge clip 4. hiperpfs 5. thermally conductive silicone grease 6. fiber washer 7. custom aluminum heatspreader 8. kapton silpad insulator to-247 9. heat sink 10. flat washer 11. lock washer 12. nut rev. a 11/09/10 16 pfs704-729eg www.powerint.com figure 17. heat sink assembly example C low power designs. figure 18. heat sink assembly C low power designs. 1. screw 2. edge clip 3. hiperpfs 4. kapton silpad insulator 5. heat sink 6. flat washer 7. lock washer 8. nut rev. a 11/09/10 17 pfs704-729eg www.powerint.com pcb design guidelines and design example the line-sense network and the feedback circuit use large resistance values in order to minimize power dissipation in the feedback network and the line-sense network. care should be taken to place the feedback circuit and the line-sense network components away from the high voltage and high current nodes to minimize any interference. any noise injected in the feedback network or the line-sense network will typically manifest as degradation of power factor. excessive noise injection can lead to waveform instability or dissymmetry. the emi flter components should be clustered together to improve flter effectiveness. the placement of the emi flter components on the circuit board should be such that the input circuit is located away from the drain node of the hiperpfs, the output diode of the pfc or the pfc inductor. a flter or decoupling capacitor should be placed at the output of the bridge rectifer. this capacitor together with the x capacitance in the emi flter and the differential inductance of the emi flter section and the source impedance, works as a flter to reduce the switching frequency current ripple in the input current. this capacitor also helps to minimize the loop figure 19. pcb layout example for system power supply consisting of a pfc and a second stage converter. area of the switching frequency current loop thereby reducing emi. the connection between the hiperpfs drain node, output diode drain terminal and the pfc inductor should be kept as small as possible. a low loss ceramic dielectric capacitor should be connected between the cathode of the pfc output diode and the source terminal of the hiperpfs. this ensures that the loop area of the loop carrying high frequency currents at the transition of switch-off of the mosfet small and helps to reduce radiated emi due to high frequency pulsating nature of the diode current traversing through the loop. during placement of components on the board, it is best to place the voltage monitor pin, feedback pin and vcc pin decoupling capacitors close to the hiperpfs before the other components are placed and routed. power supply return trace from the ground pin should be separate from the trace connecting the feedback circuit components to the ground pin. pi-6238-110810 ac input pfc output capacitor pfc output emi filter thermistor shorting relay bridge rectifier pfc inductor hiper pfs auxiliary supply for pfc C from standby power supply second stage converter rev. a 11/09/10 18 pfs704-729eg www.powerint.com to minimize effect of trace impedance affecting regulation, output feedback should be taken directly from the output capacitor positive terminal. the upper end of the line-sense resistors should be connected to the high frequency flter capacitor connected at the output of the bridge rectifer. quick design checklist as with any power supply design, all hiperpfs designs should be verifed on the bench to make sure that component specifcations are not exceeded under worst-case conditions. the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify that peak v ds does not exceed 530 v at lowest input voltage and maximum overload output power. maximum overload output power occurs when the output is overloaded to a level just above the highest rated load or before the power supply output voltage starts falling out of regulation. additional external snubbers should be used if this voltage is exceeded. in most designs, addition of a ceramic capacitor in the range of 33 pf and 100 pf connected across the pfc output diode will reduce the maximum drain-source voltage to a level below the bv dss rating. when measuring drain-source voltage of the mosfet, a high voltage probe should be used. when the probe tip is removed, a silver ring in the vicinity of the probe tip can be seen. this ring is at ground potential and the best ground connection point for making noise free measurements. wrapping stiff wire around the ground ring and then connecting that ground wire into the circuit with the shortest possible wire length, and connecting the probe tip to the point being measured, ensures error free measurement. 2. maximum drain current C at maximum ambient temperature, minimum input voltage and maximum output load, verify drain current waveforms at start-up for any signs of inductor saturation and excessive leading edge current spikes. hiperpfs has a leading edge blanking time of 220 ns to prevent premature termination of the on-cycle. verify that the leading edge current spike is below the allowed current limit for the drain current waveform at the end of the 220 ns blanking period. if a wire loop is inserted in series with the drain, it forms a small stray inductance in series with the drain. this stray inductance will add to the leading edge voltage spike on the drain source waveform. the drain- source voltage waveform should therefore never be measured with this loop. an alternate measurement that can provide drain current level and information regarding slope of the inductor current can be obtained by monitoring the inductor current instead. a wire loop can be added in series with the pfc inductor connection that connects the inductor to the input rectifer for the purpose of measurement. 3. thermal check C at maximum output power, minimum input voltage and maximum ambient temperature; verify that temperature specifcations are not exceeded for the hiperpfs, pfc inductor, output diodes and output capacitors. enough thermal margin should be allowed for the part-to-part variation of the r ds(on) of hiperpfs, as specifed in the data sheet. a maximum package temperature of 100 c is recommended to allow for these variations. 4. input pf should improve with load, if performance is found to progressively deteriorate with loading then that is a sign of possible noise pickup by the voltage monitor pin circuit or the feedback divider network and the compensation circuit. rev. a 11/09/10 19 pfs704-729eg www.powerint.com parameter symbol conditions source = 0 v; t c = -40 c to 125 c (note d) (unless otherwise specifed) min typ max units control functions maximum operating on-time t on(max) 0 c < t c < 100 c 30 40 50 m s minimum operating on-time t on(min) see note a 0 c < t c < 100 c 0 1 maximum operating off-time t off(max) 0 c < t c < 100 c 30 40 50 minimum operating off-time t off(min) 0 c < t c < 100 c 1 3 internal feedback voltage reference v ref t c = 25 c see note a 5.955 6.00 6.045 v feedback pin voltage v fb 0 c < t c < 100 c (in regulation) 5.82 6.00 6.18 v feedback pin current i fb t c = 25 c 340 500 640 na soft-start time t soft t c = 25 c 12 ms internal compensation frequency f comp see note a pole (fp) 1 khz error-amplifer gain a v see note a 100 - absolute maximum ratings drain pin peak current: pfs704 .................................. .........7.5 a pfs706 ...................................... 9.0 a pfs708 .................................... 11.3 a pfs710 .................................... 13.5 a pfs712 .................................... 15.8 a pfs714 .................................... 18.0 a pfs716 .................................... 21.0 a pfs723 ...................................... 7.5 a pfs724 ...................................... 9.0 a pfs725 .................................... 11.3 a pfs726 .................................... 13.5 a pfs727 .................................... 15.8 a pfs728 .................................... 18.0 a pfs729 .................................... 21.0 a drain pin voltage .................................. ... ..............-0.3 v to 530 v vcc and feedback pin voltage ................... .... -0.3 v to 13.4 v vcc pin current .............................................................. 25 ma voltage monitor pin voltage ................................-0.3 v to 9 v storage temperature ...................................... ..... -65 c to 150 c operating junction temperature (2) ................... -40 c to 150 c lead temperature (3) ........................................................ 260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. thermal resistance thermal resistance: e package: ( q ja ) (1) .......................... .......................... 103 c/w ( q jc )................................................ .. (see figure 20) notes: 1. mosfet only C controller junction temperature (t c ) may be less than the power mosfet junction temperature (t m ). rev. a 11/09/10 20 pfs704-729eg www.powerint.com parameter symbol conditions source = 0 v; t c = -40 c to 125 c (note d) (unless otherwise specifed) min typ max units line-sense/peak detector brown-in threshold current i uv+ 0 c < t c < 100 c 27.50 28.88 m a brown-out threshold current i uv- 0 c < t c < 100 c 22.52 24.50 m a brown-in/out hysteresis i uv(hyst) t c = 25 c 1 5.5 m a soft-start brown-out threshold current i uv-ss t c = 25 c 20.5 22.5 24.5 m a voltage monitor pin voltage threshold v v(thr) 0 c < t c < 100 c i v = i uv+ 2.3 v voltage monitor pin short-circuit current i v(sc) 0 c < t c < 100 c v v = 6 v 350 m a voltage monitor pin pre-soft-start current i v(ss) 0 c < t c < 100 c v v = 3 v 6 ma maximum line sample refresh period t refresh t c = 25 c 30 60 ms voltage monitor pin shutdown current threshold i v(off) 0 c < t c < 100 c 200 m a voltage monitor pin shutdown delay t v(off) t c = 25 c 65 110 135 m s rev. a 11/09/10 21 pfs704-729eg www.powerint.com parameter symbol conditions source = 0 v; t c = -40 c to 125 c (note d) (unless otherwise specifed) min typ max units current limit/circuit protection over-current protection i ocp pfs704 di/dt = 250 ma/ m s t c = 25 c i v < 48 m a 3.8 4.1 4.3 a i v > 59 m a 2.5 2.7 2.8 pfs706 di/dt = 300 ma/ m s t c = 25 c i v < 48 m a 4.5 4.8 5.1 i v > 59 m a 3.0 3.2 3.4 pfs708 di/dt = 400 ma/ m s t c = 25 c i v < 48 m a 5.5 5.9 6.2 i v > 59 m a 3.7 4.0 4.2 pfs710 di/dt = 500 ma/ m s t c = 25 c i v < 48 m a 6.8 7.2 7.5 i v > 59 m a 4.6 4.9 5.1 pfs712 di/dt = 650 ma/ m s t c = 25 c i v < 48 m a 8.0 8.4 8.8 i v > 59 m a 5.4 5.7 6.0 pfs714 di/dt = 800 ma/ m s t c = 25 c i v < 48 m a 9.0 9.5 9.9 i v > 59 m a 6.0 6.3 6.6 pfs716 di/dt = 920 ma/ m s t c = 25 c i v < 48 m a 9.5 10.0 10.5 i v > 59 m a 6.3 6.7 7.0 pfs723 di/dt = 250 ma/ m s t c = 25 c 3.8 4.1 4.3 pfs724 di/dt = 300 ma/ m s t c = 25 c 4.5 4.8 5.1 pfs725 di/dt = 400 ma/ m s t c = 25 c 5.5 5.9 6.2 pfs726 di/dt = 500 ma/ m s t c = 25 c 6.8 7.2 7.5 pfs727 di/dt = 650 ma/ m s t c = 25 c 8.0 8.4 8.8 pfs728 di/dt = 800 ma/ m s t c = 25 c 9.0 9.5 9.9 pfs729 di/dt = 920 ma/ m s t c = 25 c 9.7 10.2 10.7 rev. a 11/09/10 22 pfs704-729eg www.powerint.com parameter symbol conditions source = 0 v; t c = -40 c to 125 c (note d) (unless otherwise specifed) min typ max units current limit/circuit protection (cont.) soa protection time-out t ocp t c = 25 c 200 280 360 m s soa on-time t soa see note a 1 m s leading edge blanking time t leb see note a 220 ns current limit delay t il(d) see note a 100 ns leb + ild + driver delay t leb + t il(d) + t driver t c = 25 c 370 470 570 ns thermal shutdown temperature t shut see note a 111 118 126 c thermal shutdown hysteresis t hyst see note a 50 c feedback pin undervoltage fb uv t c = 25 c 3 3.5 4 v feedback pin undervoltage delay t fb(uv) t c = 25 c 65 110 135 m s feedback pin overvoltage threshold and hysteresis fb ov 0 c < t c < 100 c threshold v fb +40 mv v fb +90 mv v fb +160 mv v 0 c < t c < 100 c hysteresis 75 mv feedback pin overvoltage delay t fb(ov) t c = 25 c 1 2 3 m s feedback pin start-up threshold fb off 0 c < t c < 100 c 0.5 1.2 1.65 v feedback pin off delay t fb(off) 0 c < t c < 100 c 0.5 2 4 m s start-up v cc (rising edge) v cc+ t c = 25 c 9.5 10.2 v shutdown v cc (falling edge) v cc- t c = 25 c 9.0 9.5 v v cc hysteresis v cc(hyst) t c = 25 c 0.2 0.5 0.8 v supply current characteristics i cd1 0 c < t c < 100 c switching 3.5 ma i cd2 0 c < t c < 100 c not switching 1.5 v cc power-up reset threshold v cc(por) t c = 25 c 2.85 3.6 4.25 v v cc power-up reset current i vcc(por) t c = 25 c 1.5 ma rev. a 11/09/10 23 pfs704-729eg www.powerint.com parameter symbol conditions source = 0 v; t c = -40 c to 125 c (note d) (unless otherwise specifed) min typ max units power mosfet on-state resistance r ds(on) pfs704 i d = i ocp 0.5 see note e t m = 25 c 0.61 0.72 w t m = 100 c 1.16 pfs706 t m = 25 c 0.52 0.61 t m = 100 c 0.97 pfs708 t m = 25 c 0.41 0.48 t m = 100 c 0.77 pfs710 t m = 25 c 0.35 0.41 t m = 100 c 0.65 pfs712 t m = 25 c 0.30 0.35 t m = 100 c 0.55 pfs714 t m = 25 c 0.26 0.31 t m = 100 c 0.48 pfs716 t m = 25 c 0.22 0.26 t m = 100 c 0.42 pfs723 t m = 25 c 0.58 0.69 t m = 100 c 1.10 pfs724 t m = 25 c 0.49 0.58 t m = 100 c 0.92 pfs725 t m = 25 c 0.39 0.46 t m = 100 c 0.73 pfs726 t m = 25 c 0.33 0.39 t m = 100 c 0.62 pfs727 t m = 25 c 0.28 0.33 t m = 100 c 0.52 pfs728 t m = 25 c 0.25 0.29 t m = 100 c 0.46 pfs729 t m = 25 c 0.21 0.25 t m = 100 c 0.40 rev. a 11/09/10 24 pfs704-729eg www.powerint.com parameter symbol conditions source = 0 v; t c = -40 c to 125 c (note d) (unless otherwise specifed) min typ max units power mosfet (cont.) effective output capacitance c oss t c = 25 c, v gs = 0 v, v ds = 0 to 80% v dss see note a pfs704 176 pf pfs706 210 pfs708 265 pfs710 312 pfs712 320 pfs714 420 pfs716 487 pfs723 185 pfs724 221 pfs725 278 pfs726 328 pfs727 389 pfs728 441 pfs729 511 breakdown voltage bv dss t m = 25 c, v cc = 12 v i d = 250 m a, v fb = v v = 0 v 530 v breakdown voltage temperature coeffcient bv dss(tc) 1.2 %/c rev. a 11/09/10 25 pfs704-729eg www.powerint.com notes: a. not a tested parameter. guaranteed by design. b. tested in typical boost pfc application circuit with 0.1 m f capacitor between the v pin and g pin and a 4 m w resistor from rectifed line to the v pin for pfs70x and pfs71x. c. tested in typical boost pfc application circuit with 0.047 m f capacitor between the v pin and g pin and a 9 m w resistor from rectifed line to the v pin for pfs72x. d. normally limited by internal circuitry. e. refer to i ocp with i v <48 m a for pfs704-716. parameter symbol conditions source = 0 v; t c = -40 c to 125 c (note d) (unless otherwise specifed) min typ max units power mosfet (cont.) off-state drain current leakage i dss t m = 100 c v ds = 80% bv dss v cc = 12 v v fb = v v = 0 pfs704 80 m a pfs706 100 pfs708 120 pfs710 150 pfs712 170 pfs714 200 pfs716 235 pfs723 84 pfs724 105 pfs725 126 pfs726 158 pfs727 179 pfs728 210 pfs729 247 turn-off voltage rise time t r see note a, b, c 50 ns turn-on voltage fall time t f 100 start-up time delay t start-delay 0 c < t c < 100 c see note a, b, c 2 6 10 ms rev. a 11/09/10 26 pfs704-729eg www.powerint.com typical performance characteristics 0 pfs704 pfs723 pfs706 pfs724 pfs708 pfs725 pfs710 pfs726 pfs712 pfs727 pfs714 pfs728 pfs716 pfs729 thermal resistance jc (c/w) 3 2.5 2 1.5 1 0.5 0 pi-6234-110510 figure 20. thermal resistance ( q jc ). figure 21. typical characteristic: voltage monitor pin voltage vs. current. figure 22. typical characteristic: feedback pin current vs. voltage. 0 50 100 150 200 250 300 voltage monitor pin voltage (v) voltage monitor pin current ( a) 7 6 5 3 4 2 1 0 pi-6239-111010 0 3 2 1 4 5 7 6 8 9 10 11 12 13 14 feedback pin current (a) feedback pin voltage (v) 20 15 5 10 0 -5 pi-6240-110810 rev. a 11/09/10 27 pfs704-729eg www.powerint.com typical performance characteristics (cont.) figure 23. typical characteristic: vcc pin current vs. voltage (device not switching). 0 3 2 1 4 5 7 6 8 9 10 11 12 13 14 vcc pin current (ma) vcc pin voltage (v) 1.2 1 0.6 0.4 0.8 0.2 -5 pi-6241-111010 rev. a 11/09/10 28 pfs704-729eg www.powerint.com pi-5711-110810 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 (0.18) per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. controlling dimensions in inches (mm). esip-7g (e package) 0.378 (9.60) ref. 0.019 (0.48) ref. 0.027 (0.70) 0.023 (0.58) 0.020 (0.50) 0.060 (1.52) ref. 10 ref. all around 0.016 (0.41) ref. 0.290 (7.37) ref. detail a 0.047 (1.19) 0.050 (1.27) 0.070 (1.78) ref. pin 1 i.d. 0.118 (3.00) front view side view back view detail a end view 0.140 (3.56) 0.120 (3.05) 0.081 (2.06) 0.077 (1.96) 6 0.016 (0.41) 0.011 (0.28) 0.020 m 0.51 m c 3 0.403 (10.24) 0.397 (10.08) 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) 2 0.325 (8.25) 0.320 (8.13) 2 c a b 0.221 (5.61) ref. 0.519 (13.18) ref. 0.100 (2.54) 0.211 (5.36) ref. 0.207 (5.26) 0.187 (4.75) 6 0.033 (0.84) 0.028 (0.71) 0.010 m 0.25 m c a b 4 a a 3 mounting hole pattern (not to scale) pin 7 pin 1 0.100 (2.54) 0.100 (2.54) 0.059 (1.50) 0.059 (1.50) 0.050 (1.27) 0.050 (1.27) 0.100 (2.54) 0.155 (3.93) rev. a 11/09/10 29 pfs704-729eg www.powerint.com part marking information ? hiperpfs product family ? pfs series number ? package identifer e plastic esip-7g ? pin finish g halogen free and rohs compliant part ordering information part number option quantity pfs704eg tube 48 pfs706eg tube 48 pfs708eg tube 48 pfs710eg tube 48 pfs712eg tube 48 pfs714eg tube 48 pfs716eg tube 48 pfs723eg tube 48 pfs724eg tube 48 pfs725eg tube 48 pfs726eg tube 48 PFS727EG tube 48 pfs728eg tube 48 pfs729eg tube 48 pfs 704 e g for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperlcs, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2010, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) room 1601/1610, tower 1 kerry everbright city no. 218 tianmu road west shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg., 2070 shennan zhong rd, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokohama, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #19-01/05 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date a initial release 11/09/10 |
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